基于FPGA技术的抽取器设计与实现

                         

                                                                        

软件无线电是未来通信的发展方向，而作为其重要组成部分之一的抽取器，将难以实时处理的高速数据流变为低速率信号，使软件无线电的实现成为可能。

基于抽取器的基本原理，本文研究和分析了多种数字滤波器及抽取结构，并用MATLAB进行仿真，从而确定了本设计所采用的抽取器结构。在此基础上，采用Quartus II开发系统设计了抽取器各个模块，通过波形仿真验证了其正确性。最后，采用系统硬件平台将程序写入FPGA芯片，利用示波器和频谱分析仪对设计的抽取器进行了频域和时域性能分析。

       本文完整地完成了抽取器的设计和实现过程，从理论到实际硬件一步步验证了FPGA技术应用于抽取器的可行性及灵活性。

 

关键词：抽取器，数字滤波器，软件无线电，MATLAB，VHDL， FPGA

THE DESIGN AND IMPLEMENTATION OF

DECIMATOR BASED ON FPGA

 

 

 

 

 

Software radio is regarded as the developing direction of communication in future, and as one part of this, decimator change the high rate dataflow to a lower one, which meets the require of real-time processing and makes software radio come true.

Based on the theories of decimation, this dissertation analyses kinds of digital filters and decimation structures. With the MATLAB simulation, it determines the final structure of decimator. According to this, every module of this decimator is designed on Quartus II developing system, which is proved correct by wave simulation. At last, this design of the decimator is implemented on FPGA hardware platform, and tested by oscilloscope and spectrum analyzer.

This dissertation complete all the steps of the design and implement of decimator, and prove the possibility and flexibility of using FPGA to realize decimator both in theory and in practice.

 

Key Words: Decimation，Digital Filter，Software Radio，MATLAB，VHDL，FPGA